Ferroelectric memory devices, like other semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two -capacitor (2T2C) cell configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically include one or more ferroelectric capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices. The access transistor in a 1T1C configuration operates to selectively connect one terminal of the ferroelectric capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage and the other capacitor terminal being connected to a plateline pulse during read operations.
The ferroelectric memory cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry. Such devices are typically organized internally into blocks, sections, segments, rows and columns. When a data word is read, the cell data from the corresponding bit in each of the columns is sensed using individual sense amplifiers associated with the individual data cell columns.
Data in a ferroelectric memory cell is generally read by coupling complementary input terminals of a differential sense amp with one terminal of the cell capacitor a reference voltage. The other terminal of the capacitor is generally connected to a plateline pulse. The dipole switching in the ferroelectric capacitor resulting from the field across the ferroelectric capacitor terminals causes a switching current to flow, creating a differential voltage on the bitline pair coupled with the sense amp terminals. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1” (V“1”). The sense amp senses the differential voltage across the terminals and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”. The resulting amplified differential voltage at the sense amp terminals represents the data stored in the cell, which is applied to a pair of local IO lines. The sense amp drives one of the local IO lines to a different voltage state, by which the read data state is passed to an IO buffer circuit. The data is then restored to the ferroelectric cell capacitor, as the read operation is destructive in the sense the stored state is lost.
In a write operation, the complimentary sense amp and bitline terminals are generally connected to the local IO lines, which are driven to opposite voltage states depending on the data to be written. The wordline turns on the cell access transistor, coupling one of the ferroelectric capacitor terminals to one of the bitlines for storage of the write data into the ferroelectric capacitor, and the other capacitor terminal is connected to a plateline pulse. The applied field across the ferroelectric material in the ferroelectric capacitor provides dipole switching by which the cell is programmed according to the write data from the local IO. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local IO lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the memory device (e.g., row decoders providing plateline signals and column decoders providing wordline signals to the access transistors in a 1T1C configuration).
The various read/write operations described supra utilize the ferroelectric properties, polarization, of the ferroelectric layer. Data retention is the ability of a memory cell, particularly a non-volatile memory cell, to properly maintain stored data. Proper operation, including data retention, of ferroelectric memory devices depends on the bi-stable characteristic of the ferroelectric memory cell described above. However, over time, the bi-stable characteristic can degrade significantly and negatively affect data retention. Thus, ferroelectric memory devices can, over time, become unusable for some applications.
It is known that the ferroelectric capacitors tend to imprint or develop a “preference” for a state at which they are raised to a relatively high temperature in, also referred to as baked. The initial state at which the ferroelectric capacitors are baked in, referred to as the same state, is generally stable, but can become so stable that the capacitors can preferentially want to remain there. However, the opposite state can become unstable or un-maintainable because of this developed preference for the baked or same state. Due to assembly induced degradation, imprint detection has generally been performed post assembly (e.g. at package test).
One known way to detect imprint is to initially write same state data to the ferroelectric capacitor, then bake the ferroelectric capacitor to a relatively high temperature, such as 125° C. to 150° C. for about 10 to 24 hours. The same state data is then read. Since the read operation is destructive, a rewrite normally follows a read operation. Opposite state data (opposite to the same state) is then written. A selected period of wait time may follow for stability. A read is operation is then performed. If the opposite state data is not successfully read, the ferroelectric capacitor can be determined to be imprinted, and thus the corresponding ferroelectric memory cell may be rejected.